A major motivation for emulation is to allow instructions streams written for a particular architecture to execute on another architecture, with minimum loss of performance. Clearly then, the efficiently of the emulation process and the quality of the resulting “host” instruction sequence are of paramount importance.
Typically, a computing system includes several portions, including the processors, the memory, and the input/output devices. It is often necessary to emulate the behavior of one computing system on another. One of the principal reasons for emulation is to enable programs written for a system (e.g., the “target computing system”), to perform with the same results on another system (e.g., the “host computing system”).
The need for emulating the behavior of one computer system one another has long been recognized. Numerous schemes have been proposed for doing this. A summary of certain of these techniques appears in U.S. Pat. No. 6,031,992 to Cmelik et al. U.S. Pat. No. 6,031,992 discloses a combined hardware/software scheme to perform emulation of an instruction set of one processor on another processor. This scheme allows the hardware design to incorporate features that facilitate the execution of the target instruction set. For the same reason, however, this approach cannot emulate all systems equally efficiently.
SimOS and SimICS are emulator examples that can emulate without special hardware features. However, their performance may not be as effective as that of the method and structure of U.S. Pat. No. 6,031,992.
In general, these systems employ various levels of translation. For example, “Alpha Runs x86 Code with FX!32”, Jim Turley, Mar. 5, 1996, Microprocessor Report, describes techniques where the extent of translation is varied according to the extent of execution of the code.
In conventional emulation methods and techniques, various levels of translation may be employed to enhance the performance of the host instructions produced by the emulator. However, notwithstanding existence of these techniques, there remains need for improvement.
With an emulation approach which includes a combination of interpretation and translation, each target instruction is interpreted, a simple heuristic is employed to record frequency of execution of instruction groups, and when a threshold condition is satisfied, that group is scheduled for translation by placing it in a translation pool. This technique allows the interpretation process to proceed in parallel with the translation process, and so the translator may deploy fairly aggressive optimization techniques.
Emulation with translation amortizes the cost of optimization, and is effective for longer running, frequently executed instruction sequences. Various optimization techniques are known in the art of emulation with translation. However, additional optimizations are deemed desirable to further facilitate the process.